This invention is generally directed to a charge storage target for utilization within a pickup tube. The specific application is a target that utilizes a semiconductor wafer of a first type of conductivity with a mosaic of regions of an opposite type of conductivity to the wafer provided on one surface of the wafer and forming junctions with the wafer. The mosaic of regions forms storage sites and is scanned by a reading electron beam. Input radiation in the form of electrons or light are directed into the wafer from the opposite side with respect to the reading electron beam and generate electron-hole pairs which diffuse to the junctions formed in the wafer. The regions or junctions are separated from each other and form a rectifying junction with the semiconductor wafer or substrate. The junctions are provided with a reverse bias and the minority carriers discharge this reverse bias. The amount of electron beam current utilized by the reading beam in depositing a charge on the storage site to recharge the diode is the output signal. One specific type is described in U.S. Pat. No. 3,011,089, issued to F. W. Reynolds on November 28, 1961, and U.S. Pat. No. 3,403,284 by T. M. Buck et al. issued Sept. 24, 1968. These devices are generally referred to as diode array targets. A further extension of the light input type target is the use of a structure in which the input light image is first focused onto a photocathode and the emitted photoelectrons from a photocathode are in turn accelerated by an electric field and focused onto the front surface of the target. The carriers generated by the photoelectrons have the same function as the photogenerated carriers described above.
To allow the scanning reading electron beam to land on the individual diode regions positioned in apertures of an insulating coating without being deflected by charge which tends to build up on the surrounding insulating layer two main approaches have been utilized. The first is to cover the whole read side of the target with a resistive layer which allows this charge to leak off of the insulating coating to the diodes. Such a structure is shown in FIG. 3. A second approach is to cover most of the insulating coating with conductive contact pads which extend out from each diode region and are separated by a very narrow region of exposed oxide coating. FIGS. 4 and 5 illustrate this approach to the problem. The resistive coating approach is found to degrade the resolution of the target in that the resistive coating by its very nature is a charge leakage path which allows some discharge between adjacent diodes. A further problem associated with this approach is that a high resistance path is placed between the reading electron beam and the diodes. This makes for a less efficient recharging of the diodes and the lag of this type of target tends to be relatively high.
The second approach illustrated in FIG. 4 utilizes conductive p+ silicon bumps or contacts which are grown epitaxially. This approach overcomes the leakage between the diode problems and also does not have a disadvantage of the beam resistance of the previous approach. The disadvantage of the structure as shown in FIG. 4 is the sloping sides of the contact, limit the height that the contacts can be grown since the contacts must not touch. Another modification of the second approach is illustrated in FIG. 5 and has the advantages of FIG. 4 but the disadvantages that the fabrication process requires a second photomask step for delineation of the conducting pads.